发明名称 |
Transmitter, receiver, and communication method |
摘要 |
Separation circuit 250 separates a systematic bit and parity bit from a received packet. Combination circuit 204 symbol-combines the separated systematic bit in this retransmission unit with systematic bits acquired in preceding retransmission units. Then, decoder 214 likelihood-combines the separated parity bit with parity bits acquired in preceding retransmission units and performs error correcting decoding on the symbol-combined systematic bit using the likelihood-combined parity bit as a check bit. This makes it possible to increase the reception level and error correcting performance, reduce the number of times retransmission is carried out until all errors are eliminated and thereby improve throughput.
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申请公布号 |
US2003014709(A1) |
申请公布日期 |
2003.01.16 |
申请号 |
US20020182531 |
申请日期 |
2002.07.31 |
申请人 |
MIYOSHI KENICHI;MATSUMOTO ATSUSHI |
发明人 |
MIYOSHI KENICHI;MATSUMOTO ATSUSHI |
分类号 |
H04L27/00;H04J13/02;H04L1/00;H04L1/16;H04L1/18;H04L27/22;H04L29/02;(IPC1-7):H04L1/18;G08C25/02;H03M13/00 |
主分类号 |
H04L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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