发明名称 Pattern layout of transfer transistors employed in row decoder
摘要 A semiconductor memory device comprises a memory cell array, a block select circuit, a plurality of word-line-driving-signal lines, and a plurality of transfer transistors. The memory cell array includes a plurality of blocks, each of the blocks including memory cells arranged in rows and columns. The block select circuit selects one of the blocks of the memory cell array. The word-line-driving-signal lines receive voltages to be applied to a plurality of word lines in each block. The transfer transistors are connected between the word-line-driving-signal lines and the word lines of the memory cell array, and are controlled by outputs from the block select circuit. Any two of the transfer transistors, which correspond to each pair of adjacent ones of the word lines, are separate from each other lengthwise and widthwise, and one or more transfer transistors corresponding to another word line or other word lines are interposed therebetween.
申请公布号 US6507508(B2) 申请公布日期 2003.01.14
申请号 US20010984960 申请日期 2001.10.31
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 HOSONO KOJI;NAKAMURA HIROSHI;IMAMIYA KENICHI;TANAKA TOMOHARU
分类号 H01L21/8247;G11C8/08;G11C8/10;G11C16/04;G11C16/08;H01L27/10;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C5/06 主分类号 H01L21/8247
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