Method and apparatus for latching a clocked data signal

摘要

A latch includes memory and pulldown circuitry coupled to nodes of the memory for pulling one of the nodes down responsive to data. The pulldown circuitry has gating circuitry for gating the pulling down responsive to a clock signal. The latch also has pull up circuitry coupled to the other one of the memory nodes. A first pull up circuitry section is operable to pull the other one of the memory nodes up to a high state responsive to data. The first pull up circuitry section includes second gating circuitry. The second gating circuitry is operable to gate the pulling up of the other one of the memory nodes responsive to a pull up circuitry clock signal. The first pull up circuitry section more quickly pulls up its memory node, so that the two nodes are pulled up and down at more nearly the same time.