发明名称 |
Integrated circuit memory having column redundancy |
摘要 |
A memory array has memory elements arranged in rows and columns. Each column has a respective bit line. A plurality of bit line input-output nodes are each switchably coupled to either a respective one of the bit lines or another one of the bit lines.
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申请公布号 |
US6507524(B1) |
申请公布日期 |
2003.01.14 |
申请号 |
US20000727043 |
申请日期 |
2000.11.30 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
AGRAWAL GHASI;WIK THOMAS R. |
分类号 |
G11C29/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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