发明名称 |
MOS transistor and fabrication method thereof |
摘要 |
A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.
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申请公布号 |
US6507080(B2) |
申请公布日期 |
2003.01.14 |
申请号 |
US20010761902 |
申请日期 |
2001.01.17 |
申请人 |
FAIRCHILD KOREA SEMICONDUCTOR LTD. |
发明人 |
JANG KYUNG-OUN;LEE SUN-HAK |
分类号 |
H01L21/8238;H01L27/092;H01L29/08;H01L29/10;H01L29/423;H01L29/78;(IPC1-7):H01L29/72 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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