Semiconductor memory device including plural blocks with selecting and sensing or reading operations in different blocks carried out in parallel

摘要

A memory device includes a plurality of blocks, each being capable of carrying out different types of operations, and a control unit for selecting one block after another from the plurality of blocks. In this memory device, each selected block upon a selection thereof starts carrying out the operations in a predetermined order in a pipeline operation. The memory device may include an array of memory cells, a word line selecting circuit, a row address register circuit, sense amplifiers, a precharge circuit, a global row scheduler for successively selecting two or more blocks to simultaneously perform respective operations, and a check unit. The check unit detects consecutive accesses that are made by the global row scheduler to a single block, thereby causing the global row scheduler to delay or ignore the block selection of the single block.