| 摘要 |
PURPOSE: A digital phase interpolation circuit for controlling a delay time and a method for controlling the delay time are provided to reduce the overall area and the current consumption thereof by constructing the number of inverters with the same at each of the stages although the number of the stages are increased in response to the number of minimum delay steps. CONSTITUTION: A digital phase interpolation circuit for controlling delay times of a first signal and a second signal, wherein each of the signals having a different phase delay, includes a pair of inverters(300,305) and N number of delay stages(310-330), wherein each of the delay stages(310-330) includes a first inverting block for converting the first and the second input signal inputted from the previous stage, respectively, a phase mixing block for outputting the first to Nth phase mixing signals, respectively, by mixing the phases of the mixed first and second input signals, a second inverting block for inverting the output signals of the first inverting block and a multiplexor for applying a first and a second input signal of the following stage by determining one of the first and the second input signals outputted from the second inverting block and the phase mixing signal of the corresponding stage among the first to Nth phase mixing signals in response to the predetermined selection signal to determine the phase delay of the output signals as a phase interpolation axis and for applying the phase interpolation axis as a first and a second input signals of the following stage.
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