发明名称 CLOCK STABILIZATION DEVICE OF DUPLEX CLOCK SUPPLYING SOURCE
摘要 PURPOSE: A clock stabilization device of a duplex clock supplying source is provided to stably supply a clock without shorting the continuity of system clock in case of the operation mode between clock supplying sources by mis-operating the activated clock supplying sources. CONSTITUTION: A clock stabilization device of a duplex clock supplying source includes a plurality of clock supply sources(311,312) for generating a clock signal having a predetermined frequency, a plurality of clock detection circuits(321,322) for detecting whether the clock signal generated at each of the clock supply sources(311,312) are fail or not, a clock signal delay block(330) for delaying the clock signal generated at each of the clock supply sources(311,312) by a predetermined delay time and for outputting the delayed clock signals, a control circuit block(340) for outputting a control signal so as to the clock signal generated at each of the clock supply sources(311,312) to an external system by receiving the detection signals of each of the clock detection circuits(321,322) and a multiplexing block(350) for selecting one among the clock signals outputted from the clock signal delay block(330) in response to the control signal of the control circuit block(340) and for applying the selected clock signal to the external system.
申请公布号 KR20030003944(A) 申请公布日期 2003.01.14
申请号 KR20010039814 申请日期 2001.07.04
申请人 LG ELECTRONICS INC. 发明人 PARK, NAM JU
分类号 H03K3/00;(IPC1-7):H03K3/00 主分类号 H03K3/00
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