SEMICONDUCTOR MEMORY DEVICE HAVING ECHO CLOCK PATH

摘要

PURPOSE: A semiconductor memory device is provided to efficiently remove skew between an echo clock from an echo clock generator and data from a memory cell during a test mode of operation. CONSTITUTION: A cell data output part(10) senses and amplifies cell data in a memory cell array and the amplified data to an input/output pad in synchronization with a data enable clock signal(KDATA). An echo clock generator(12) receives a power supply voltage(VDD) and a ground voltage(GND) and generates an echo clock synchronized with the data enable clock signal(KDATA). An output data clock driver(14) generates the data enable clock signal(KDATA) synchronized with rising and falling edges of an external system clock. A variable delay(16) has a plurality of delay paths for delaying the data enable clock signal(KDATA), and selects one of the delay paths in response to a select signal to provide a signal from a selected delay path to the cell data output part(10) and the echo clock generator(12). A fuse array outputs the select signal to variable delay(16). A test controller(40) outputs a delay path test code(DTC) for selecting a delay path corresponding to a test code(TC), and outputs a mode select signal(MSEL). A fuse array and multiplexor(42) have at least two fuses for selecting one of delay paths of the variable delay(16), and selectively provide the test code(TC) and the programmed select signal to the variable delay(16), based on the test mode signal.