| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit that causes less data error even in the case of high-speed data, has less possibility of affection of noise due to an external disturbance and can attain high-speed locking at rising of a system employing the PLL circuit. SOLUTION: A phase comparator circuit detects a phase difference between a reference input signal and a subordinate frequency signal, generates a pulse width in response to a detected value, and sums the pulse width and a phase comparison result in terms of levels so as to quicken the response of fluctuations thereby reducing phase fluctuations and steady-state phase difference fluctuations, a consecution detection circuit 110 detects the consecutive state of a large phase difference when the system arises and the phase difference is large, allows a DFF(D type flip-flop) 117 or 118 to generate consecutive phase lead/lag detection signals S21, S22 depending on the detection state and to forcibly fix a pulse modulation output S7 to have a duty ratio of 0 or 1. |
