| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock phase adjustment circuit that adjusts the phase of a sampling clock for an analog/digital converter so that a phase deviation between the sampling clock for analog/digital converter and an analog input signal is zeroed and a sampling point comes to the center point of the analog input signal. SOLUTION: A level coincident detector 16 detects coincidence in terms of a difference between a difference level from a detector 14 and a reference level from a detector 15, a phase coincidence discrimination circuit 17 for collecting a plurality of pixels for detection of partial coincidence to provide the output of phase coincidence decision, a retrieval phase control signal generating circuit 21 integrates the discrimination results by its built-in counter to generate a retrieval use phase control signal, a signal center position arithmetic circuit 22 calculates about the median of the phase coincidence point to output a corresponding phase control signal and to discriminate whether or not the retrieval is made and controls a switching circuit 23 by a discrimination signal so as to select a phase control signal corresponding to the nearly median of the phase coincidence point from the retrieval phase control signal and provide an output of the selected signal to a phase quantity adjustment device 19 to adjust the phase of the sampling clock of the analog/digital converter 13.
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