| 摘要 |
PROBLEM TO BE SOLVED: To reduce scale of circuits of a data storage circuit in which the data width of a data input and a data output is freely changeable up to several times. SOLUTION: In this data processor, memory cells from and to which bit data having (a) bits are read and written are selected in a cell selecting circuit according to address data, but, a number of pieces changeover circuit changes over and sets the number of pieces of memory cells according to a selection signal. As a result, it is possible to change over and set the data width of the data input and the data output having (a) bits to B times with a piece of a data storage circuit and thus it is not necessary to provide B pieces of data storage circuit having data widths of (a) bits in parallel in the data processor. |
