发明名称 CONTROL METHOD OF POWER DOWN VOLTAGE, DEVICE, AND SEMICONDUCTOR MEMORY HAVING THE DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method and a device for controlling power down voltage by which DPD entry and DPD leaving can be performed with the minimum current variation, and to provide a semiconductor memory having the device. SOLUTION: A device for controlling entry to DPD and leaving from DPD of a semiconductor memory comprises a plurality of voltage generators providing operation voltage to the semiconductor memory, a DPD controller sensing a DPD state and generating a DPD signal to control application of the operating voltage for the semiconductor memory, and a bias circuit biasing a plurality of nodes of at least one voltage generator out of the plurality of voltage generators to at least one prescribed voltage potential to prevent an erroneous trigger of a circuit in DPD mode entry/leaving.
申请公布号 JP2003007061(A) 申请公布日期 2003.01.10
申请号 JP20020129006 申请日期 2002.04.30
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 CHOI JONG-HYEON;YOO JAE-HWAN;LEE JONG-EON;JANG HYUN-SOON
分类号 G11C11/407;G11C5/14;(IPC1-7):G11C11/407 主分类号 G11C11/407
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