| 摘要 |
PROBLEM TO BE SOLVED: To reduce the scale of circuits and the chip area of the memory featured with an error-correcting function. SOLUTION: This memory is provided with a data holding circuit 4 holding he output data of an error detecting and correcting circuit 3 in synchronization with an initialized clock signal, a selection circuit 5 selecting the output of the data holding circuit 4 as the input data of an error-correcting code generating circuit 1 at a test mode operation, a code changing circuit 6 which inputs an error-correcting code form the error-correcting code generation circuit 1 and changes the code by inverting respective bits of the code with a sequentially changing merge bit and a selection circuit 7 selecting outputs of the data holding circuit 4 and the code changing circuit 6 as the input data and the input error- correcting code of the error detection and correction circuit 3 at the test mode operation. |
