| 摘要 |
PROBLEM TO BE SOLVED: To minimize the deterioration of a plotting access speed from a CPU to a display memory due to access from a display control circuit to the display memory, and to maximize the performance of the plotting access from the CPU. SOLUTION: A CPU I/F 11, a plotting control circuit 12, a display control circuit 13, a panel I/F 14, a VRAM memory access arbitrating circuit 17, a VRAM 18, a display timing control circuit 19, a CPU bus arbitrating circuit 15, and a display control setting circuit 16 are integrated on one semiconductor chip, and the CPU I/F 11 outputs a bus release request signal 101 to a CPU 2 in response to an access request from the display control circuit 13 to the VRAM 18 without requesting any additional time or clock to the bus access to the CPU 2, and performs the memory access to the VRAM 18 for display while approving the bus release at the time of receiving a bus release approval signal 102 from the CPU 2.
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