发明名称 |
Evaluation circuit for a DRAM |
摘要 |
A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.
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申请公布号 |
US2003007391(A1) |
申请公布日期 |
2003.01.09 |
申请号 |
US20020190814 |
申请日期 |
2002.07.08 |
申请人 |
BEER PETER;SCHAFFROTH THILO |
发明人 |
BEER PETER;SCHAFFROTH THILO |
分类号 |
G11C7/06;G11C7/18;G11C11/4091;G11C11/4097;(IPC1-7):G11C5/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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