摘要 |
A complex vector operation processor for carrying out a complex vector operation includes first and second multiplier sections, first to third adder sections, and a data output section. The first and second multiplier sections are provided in parallel. The first adder section is operatively connected with outputs of the first and second multiplier sections. The second and third adder sections are operatively connected with output of the first adder section and arranged in parallel. The data output section is operatively connected with the second and third adder sections to produce complex operation resultant data.
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