| 摘要 |
The present invention is a method for manufacturing a non-volatile semiconductor memory cell of a structure provided with a trap gate between a word line serving as a control gate, and a channel region of a substrate, the trap gate is constructed of an insulating layer and capable of trapping a carrier. The trap gate constructed of the insulating layer can change a threshold of a transistor locally because the carriers injected and trapped inside do not move in the gate. As associated with it, the trap gate does not need to be separated between adjacent memory cells. In addition, the insulating layers for electrical isolation need to be formed on and under the trap gate constructed of the insulating layer. However, the gate insulating layer of the three-layers structure can be formed very thin and highly reliably compared with the conventional floating gate structure. According to the present invention, the manufacturing method comprises the steps of forming a striped pattern extending in the word line direction; depositing an insulating film on the striped pattern and then forming a side wall insulating film on both side walls of the striped pattern by etching the surface throughout; selectively removing the striped pattern and then depositing a gate insulating film including a trap gate insulating film on an exposed substrate; and depositing a conductive layer throughout on the surface and removing the upper part of the conductive layer except for a region between the side wall insulating films. Consequently, the conductive layer between the side wall insulating films becomes the word line.
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