| 摘要 |
PURPOSE: A pulse train generator using a shift register is provided to generate a single pulse having a width of T and a pulse train having a period of N(N-1) using an N bit shift register and (N-1) bit shift register. CONSTITUTION: A bit shift controller(31,32,33,34) designates a shift start location of an external pulse train. A first D-flip flop(31) receives a reference clock and an input pulse. A second D-flip flop(32) receives a non-inverting output of the first D-flip flop(31) and a logic 1 through clock and input terminals thereof, respectively. An inverter(33) inverts a non-inverting output of the second D-flip flop(32). A first AND gate(34) ANDs an output of the inverter(33) and a non-inverting output of the first D-flip flop(31). A bit shift section(35,36,37,38,39) bit-shifts the external pulse train from the shift start location and generates a pulse train having a predetermined period. A first OR gate(35) ORs an output of the first AND gate(34) and an output of an (N-1) bit shift register(37). A second OR gate(36) ORs an output of the AND gate(34) and an output of an N bit shift register(38). The (N-1) bit shift register(37) receives an output of the first OR gate(35) and a reference clock. The N bit shift register(38) receives an output of the second OR gate(36) and the reference clock. A second AND gate(39) ANDs outputs of the (N-1) bit shift register(37) and N bit shift register(38).
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