| 摘要 |
PURPOSE: A static random access memory(SRAM) device is provided to reduce the cell area of an SRAM device and suppress an increase of amplification delay in its bit line by including one set of drive and access transistors having almost the same channel widths wherein the channel widths are larger than those of the other set of drive and access transistors. CONSTITUTION: A complementary metal oxide semiconductor(CMOS) SRAM has its memory cell comprising six transistors. The channel widths(gate widths) of drive and access transistors(MN1,MN3) which constitute one of the two sets of CMOS inverters are made nearly equal to each other and are made larger than the channel widths of drive and access transistors(MN0,MN2) which constitute the other of the two sets of CMOS inverters. Between the basic circuits comprising the two sets of CMOS inverters, the off-leakage currents of the inverters are made unsymmetrical to cut down the leakage current of the SRAM device which is generated in its waiting time, while securing the large cell-current of one of the two sets of CMOS inverters.
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