| 摘要 |
A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. The decoder further includes a number of single crystalline ultra thin vertical transistor that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A plurality of buried source lines formed of single crystalline semiconductor material are disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array. And, each of the number of address lines is disposed in a trench between rows of the pillars for addressing the ultra thin single crystalline vertical body regions of the single crystalline vertical transistors that are adjacent to the trench.
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