发明名称 |
Detailed method for routing connections using tile expansion techniques and associated methods for designing and manufacturing VLSI circuits |
摘要 |
Disclosed herein is a method and associated apparatus for the design and manufacture of VLSI circuit which incorporates therein a method for routing connections between component tiles of the VLSI circuit being designed.
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申请公布号 |
US2003009737(A1) |
申请公布日期 |
2003.01.09 |
申请号 |
US20020119173 |
申请日期 |
2002.04.08 |
申请人 |
XING ZHAOYUN |
发明人 |
XING ZHAOYUN |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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