| 摘要 |
A microprocessor (10) configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit (12), and instruction cache (16), a data cache (28), and a level two cache (50). The predecode unit received instruction bytes and generates corresponding predecode information that is stored in the instruction cache with the instruction bytes. The data cache received and stores data bytes. The level two cache is configured to receive and store victimized instruction bytes from the instruction cache along with parity information and predecode information, and victimized data bytes from the data cache along with error correction code bits. Indicator bits may be stored on a cache line basis to indicate the type of data is stored therein.
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