发明名称 |
Glitchless clock output circuit and the method for the same |
摘要 |
A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.
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申请公布号 |
US2003006808(A1) |
申请公布日期 |
2003.01.09 |
申请号 |
US20020151923 |
申请日期 |
2002.05.22 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
WENG CHIH HSIEN;WU CHENG-YUAN;HSI CHEN-HUA |
分类号 |
G06F1/08;H03L7/081;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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