发明名称 METHOD FOR FABRICATING METAL INTERCONNECTION
摘要 PURPOSE: A method for fabricating a metal interconnection is provided to reduce resistance of a via hole by making the contact area between a plug to be formed in the via hole and the first metal interconnection extend to a corner portion of the first metal interconnection, and to prevent a void by improving the step coverage in a process for forming the plug. CONSTITUTION: An interlayer dielectric(35) is formed on an insulation substrate(31) insulated by an insulation layer, electrically connected to the metal interconnection(33). The interlayer dielectric is selectively etched to form the via hole(39) by using a via contact mask while being misaligned to expose the corner portion of the metal interconnection. A rounding etch process is performed on the corner portion of the metal interconnection exposed through the via hole by using the interlayer dielectric as a mask.
申请公布号 KR20030002525(A) 申请公布日期 2003.01.09
申请号 KR20010038174 申请日期 2001.06.29
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHO, JIN YEON
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
代理机构 代理人
主权项
地址