| 摘要 |
<p>PURPOSE: A clock synchronizing device is provided, which improves a jitter characteristics even though a low frequency clock signal is inputted, by making a constant phase resolution. CONSTITUTION: A phase detection unit(10) compares phases of an external clock signal and an internal clock signal, and a code generation unit(20,30) generates a code value of N bit according to an output signal of the phase detection unit. A digital/analog conversion unit outputs a voltage corresponding to the code value of the N bit of the code generation unit. A level detection unit(70) compares a reference voltage with the voltage being output by the digital/analog conversion unit, and then outputs a control signal controlling an output voltage value of the digital/analog conversion unit according to the comparison result. And a clock synchronization control unit outputs an internal clock signal by delaying the external clock signal according to a voltage generated by the digital/analog conversion unit. The digital/analog conversion unit comprises a main digital/analog conversion unit(50) outputting a voltage corresponding to upper N-M bit of the code value of the N bit, and a sub digital/analog conversion unit(60) outputting a voltage corresponding to a lower M bit by being enabled according to a control signal of the level detection unit.</p> |
