INNER POWER VOLTAGE GENERATION CIRCUIT AND SRAM FOR INTENSIFYING DATA RETENTION

摘要

PURPOSE: An inner power voltage generation circuit and an SRAM for intensifying data retention is provided to improve the capability of data retention at a data retention mode with maintaining a reliability for a thin gate oxide layer of a second region of a transistor to apply for the inner power voltage generation circuit. CONSTITUTION: An inner power voltage generation circuit and an SRAM for intensifying data retention includes a reference ratio voltage drop block(400) for supplying the inner power voltage by dividing a predetermined external power voltage by a reference ratio, a constant difference voltage drop block(500) for supplying the inner power voltage by dropping the external power voltage by the predetermined protection voltage and a voltage non-drop block(600) for supplying the inner power voltage by non dropping the external power voltage. The inner power voltage is supplied from the reference ration voltage drop block(400) at a predetermined interval(I) at which the external power voltage is higher than the first reference voltage and at a predetermined interval(II) at which the external power voltage is lower than the first reference voltage and higher than a second reference voltage and supplied from the voltage non-drop block(600) at a predetermined interval(III) at which the external power voltage is lower than a third reference voltage.