发明名称 |
Darc layer for MIM process integration |
摘要 |
A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.
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申请公布号 |
US2003008467(A1) |
申请公布日期 |
2003.01.09 |
申请号 |
US20010900398 |
申请日期 |
2001.07.09 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
KAI SHAO;PING WU-GUAN;LIANG CHEN;HUA CHENG-WEI;CHU SANFORD;YEN DANIEL |
分类号 |
H01L21/02;H01L21/311;H01L21/3213;(IPC1-7):H01L21/20;H01L21/476 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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