发明名称 DIGITAL PHASE INTERPOLATOR FOR CONTROLLING DELAY TIME AND METHOD THEREOF
摘要 A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.
申请公布号 US2003006817(A1) 申请公布日期 2003.01.09
申请号 US20010987624 申请日期 2001.11.15
申请人 SEO IL-WON;KIM KYU-HYUN 发明人 SEO IL-WON;KIM KYU-HYUN
分类号 H03K5/00;H03K5/13;H03L7/081;(IPC1-7):H03H11/26 主分类号 H03K5/00
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