发明名称 METHOD FOR FORMING METAL INTERCONNECTION
摘要 PURPOSE: A method for forming metal interconnection is provided to prevent a micro-loading effect by using a double film made of aluminum and tungsten as metal lines and a plug and to prevent voids without forming a via hole. CONSTITUTION: The first metal line is formed on a substrate by sequentially stacking the first barrier film(33), the first aluminum film(35), the second barrier film(37), the first tungsten film(39) and the third barrier film. At this time, the first aluminum film(35) is used as etch stopper of the first tungsten film(39). After forming the first interlayer dielectric(45), a plug on which the fourth barrier film(47), the second aluminum film(49), the fifth barrier film(51) and the second tungsten film(53) is sequentially stacked is formed. At this time, the second aluminum film(49) is used as etch stopper of the second tungsten film(53). After forming the second interlayer dielectric(59) on the resultant structure, The second metal line is formed by sequentially stacking the seventh barrier film(61), the third aluminum film(63), the eighth barrier film(65), the third tungsten film(67) and the ninth barrier film on the second interlayer dielectric. At this time, the third aluminum film(63) is used as etch stopper of the third tungsten film(67).
申请公布号 KR20030002232(A) 申请公布日期 2003.01.08
申请号 KR20010038996 申请日期 2001.06.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, GIL HO
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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