| 摘要 |
PURPOSE: A DLL circuit utilizing a bi-directional delay is provided to improve an efficiency of bi-directional delay more than doubled as well as to drastically improve an area over head by reducing the chip size thereof. CONSTITUTION: A DLL circuit utilizing a bi-directional delay includes an input buffer(30) for outputting a clock signal(CLK) and a half clock signal(CLKB) by inputting the clock signal(CLK) and the half clock signal(CLKB), a clock generation block(31) for outputting a backward signal(BWD), a replica block(32) for outputting a first signal(CLKR) and a second signal(CLKF) delayed from the clock signal(CLK) and the half clock signal(CLKB) by an excess time(tAC), respectively, a logic circuit(33) for outputting a first to a fourth delay control signals(ICLKRF,ICLKRB,ICLKFF,ICLKFB) synchronized with the two input signals, a first delay chain block(34) for outputting a first forward delay signal(OCLKRF) and a first backward delay signal(OCLKRB) by inputting the forward signal(FWD), the backward signal(BWD), the first control signal(ICLKRF) and the second control signal(ICLKRB), a second delay chain block(35) for outputting a second forward delay signal(OCLKFF) and a second backward delay signal(OCLKFB) by inputting the forward signal(FWD), the backward signal(BWD), the third control signal(ICLKFF) and the fourth control signal(ICLKFB), a first operating block(36a) for outputting a first output signal by receiving the first forward delay signal(OCLKRF) and the first backward delay signal(OCLKRB) and a second operating block(36b) for outputting a second output signal by receiving the second forward delay signal(OCLKFF) and the second backward delay signal(OCLKFB).
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