| 摘要 |
PURPOSE: A register controlled delay locked loop(DLL) is provided, which reduces the number of unit delay devices of a delay line to compensate a delay. CONSTITUTION: According to the register controlled delay locked loop, a clock divider unit generates a delay monitoring clock(dly_in) by dividing an internal clock(rise_clk) synchronized to a clock edge of an external clock. A clock generation unit generates a reference clock(ref_new) having a phase difference as much as a half period of the external clock from the delay monitoring clock. A delay model(43) reflects a delay condition of an actual internal clock path to the delay monitoring clock. A phase comparison unit(39) compares an output signal of the delay model with a phase of the reference clock. And a delay monitoring unit controls the delay amount of the delay monitoring clock and the internal clock in response to the comparison result of the phase comparison unit.
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