| 摘要 |
PURPOSE: A method for fabricating a semiconductor device is provided to improve yield by decreasing a defective flow of DC current caused by a chemical mechanical polishing(CMP) process for planarizing an interlayer dielectric before a metal interconnection is formed. CONSTITUTION: An active region and a field region are defined in a semiconductor substrate(21). An isolation layer(22) is formed in the field region of the substrate. A gate electrode is formed in the active region of the substrate insulated by the isolation layer. The first interlayer dielectric is formed on the entire surface including the gate electrode. A bitline(26) is formed on the first interlayer dielectric, electrically connected to the gate electrode and the active region of the substrate. The second interlayer dielectric(28) is formed on the resultant structure including the bitline. A lower electrode(29), a dielectric layer(30) and an upper electrode(31) are sequentially formed on the second interlayer dielectric, electrically connected to the active region of the substrate. The third interlayer dielectric(32) is formed on the resultant structure including the upper electrode and is planarized by a CMP process. The fourth interlayer dielectric(33) is formed on the third interlayer dielectric. A multilayered interconnection is formed on the fourth interlayer dielectric.
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