发明名称 |
METHOD FOR FABRICATING DUMMY PATTERN |
摘要 |
PURPOSE: A method for fabricating a dummy pattern is provided to improve yield and an electrical characteristic by basically preventing contamination caused by particles and contact resistance caused by the dummy pattern used in forming a plug by a selective epitaxial growth(SEG) method. CONSTITUTION: A gate electrode(31) and a hard mask(32) are sequentially formed on a substrate(30) which has passed through a predetermined process. An etch barrier layer(33) and an interlayer dielectric(34) are sequentially formed on the resultant structure. The interlayer dielectric is selectively etched to form a contact hole(35) exposing the upper portion of the substrate. A dummy photoresist pattern is formed on the resultant structure including the contact hole. The interlayer dielectric is etched by using the dummy photoresist pattern as a mask so that the interlayer dielectric has selectivity with the hard mask. An SEG method is used to form a plug filling the contact hole.
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申请公布号 |
KR20030001580(A) |
申请公布日期 |
2003.01.08 |
申请号 |
KR20010036357 |
申请日期 |
2001.06.25 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
HWANG, CHANG YEON;SEO, WON JUN |
分类号 |
H01L21/283;(IPC1-7):H01L21/283 |
主分类号 |
H01L21/283 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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