| 摘要 |
PURPOSE: A method for fabricating a gate for reducing a leakage current is provided to reduce junction leakage caused by stress of a nitride layer by forming the gate to make a silicon substrate directly contact the nitride layer, and to improve a hot carrier characteristic by decreasing an interfacial defect. CONSTITUTION: Polysilicon(1), tungsten(2) and the nitride layer are sequentially deposited on the silicon substrate having a cell region and a peripheral circuit region by interposing a gate oxide layer. The stacked layers are patterned to be a predetermined gate pattern through a photolithography process wherein only a half of the thickness of the polysilicon layer is etched. A predetermined thickness of a sealing nitride layer(5) is deposited on the entire surface of the substrate. A spacer etch process is performed to eliminate the remaining polysilicon layer while the sealing nitride layer is left only on the side surface of the gate. The first spacer oxide layer, a spacer nitride layer and the second spacer oxide layer are sequentially deposited on the entire surface of the substrate. A spacer etch process is performed to form a spacer on the side surface of the gate while the first spacer oxide layer in the cell region is left. A nitride layer is deposited on the entire surface of the substrate.
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