发明名称 |
METHOD FOR FORMING MULTILAYER WIRING BY DUAL DAMASCENE PROCESS |
摘要 |
PURPOSE: A method for forming multilayer wiring using dual damascene process is provided to prevent increasement of capacitance value and to restrain profile distortion at edges of a trench by remaining an etch stop pattern adjacent to a via hole. CONSTITUTION: The first metal wiring(35) is formed on a semiconductor substrate(31). The first interlayer dielectric(36) and an etch stopper are sequentially formed on the first metal wiring(35). A via hole(43a) is formed to expose the surface of the first metal wiring(35) by selectively etching the etch stopper and the first interlayer dielectric(36). An etch stop pattern(37a) remains adjacent to the via hole(43a) by selectively etching the etch stopper. After forming the second interlayer dielectric(41) on the resultant structure, a trench having a wide width compared to the via hole(43a) is formed by selectively etching the second interlayer dielectric(41). Then, the second metal wiring(43) is filled into the trench and the via hole.
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申请公布号 |
KR20030002037(A) |
申请公布日期 |
2003.01.08 |
申请号 |
KR20010038772 |
申请日期 |
2001.06.30 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM, SANG IK;LEE, SEONG GWON |
分类号 |
H01L21/3205;G03F7/00;H01L21/768;(IPC1-7):H01L21/320 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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