发明名称 |
SCAN TEST CIRCUIT AND METHOD OF SCAN-TESTING |
摘要 |
PROBLEM TO BE SOLVED: To execute testing of timing of a high speed LSI by scan-testing. SOLUTION: Scanning-in of test data D1-D6 is executed in synchronism with a clock having a frequency lower than an actual operation speed of an LSI 1. A loop is formed among an output of a scan chain 120, a selector 201, and an input of the scan chain 120. The test data D1-D6 subjected to the scanning-in is circulated on the loop for a predetermined time period in synchronism with a clock having a frequency equal to the actual operation speed of the LSI 1. The tested results R1-R6 are captured in synchronism with the clock having the frequency equal to the actual operation speed of the LSI 1. Scanning-out of the tested results R1-R6 is executed in synchronism with the clock having the frequency lower than the actual operation speed of the LSI 1. |
申请公布号 |
JP2003004807(A) |
申请公布日期 |
2003.01.08 |
申请号 |
JP20010185050 |
申请日期 |
2001.06.19 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
MATSUMOTO YOSHIFUMI |
分类号 |
G01R31/28;G06F11/22;H01L21/822;H01L27/04 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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