| 摘要 |
PURPOSE: A method for fabricating a plug of a semiconductor device is provided to guarantee resolution and an overlay margin in a design process and an exposure process by enabling a cell plug etch process, and to minimize a loss in a wordline and an isolation region by performing a high selectivity etch process on oxide or nitride. CONSTITUTION: An active region and a field region are defined in a semiconductor substrate(21). An isolation layer(22) is formed in the field region of the substrate. A plurality of gate electrodes(24) and a plurality of gate cap insulation layers(25) are formed in the active region of the substrate by interposing a gate insulation layer(23), separated from each other by a uniform interval. An insulation layer sidewall(26) is formed on both side surfaces of the gate electrode and the gate cap insulation layer. A polysilicon layer is deposited on the resultant structure including the gate electrode and is planarized to form a polysilicon plug(27a) on the substrate between the gate electrodes. A mask layer is formed on the polysilicon plug. The polysilicon layer remaining on the isolation layer is firstly etched by a sloped profile etch process using high density plasma while the mask layer is used as a mask. The polysilicon layer remaining on the insulation layer sidewall and on the bottom of the insulation layer sidewall is secondly etched.
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