发明名称 |
SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TESTER |
摘要 |
PROBLEM TO BE SOLVED: To correctly detect a phase relation of outputs of a device to be measured without effects of skew of an IC tester between pins and surely detect the phase relation of outputs of the device to be measured even when an output timing of the device to be measured changes. SOLUTION: A phase detection circuit 20 inputs an output clock D1 of the device 1 to be measured and an output data D2 of the device to be measured, and outputs the output data D2 by triggering the output data D2 by the output clock D1. A D flip flop 17 outputs the output of the phase detection circuit 20 by triggering the output by a detection strobe signal STB. An expectation comparison circuit 18 compares the output of the D flip flop 17 with expectation data.
|
申请公布号 |
JP2003004821(A) |
申请公布日期 |
2003.01.08 |
申请号 |
JP20010190790 |
申请日期 |
2001.06.25 |
申请人 |
HITACHI ELECTRONICS ENG CO LTD |
发明人 |
SAKURAI HIROYUKI |
分类号 |
G01R31/319;G01R31/28;(IPC1-7):G01R31/319 |
主分类号 |
G01R31/319 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|