| 摘要 |
With respect to a desired gate electrode (A) and dummy gate electrodes (B, C), side wall spacers (3a, 3b, 3c) of the respective gate electrodes are formed by dry etching such as an RIE method, and the etching characteristic at the time of formation of the side wall spacer is utilized so that the side wall spacer width of the desired gate electrode is controlled by adjusting gap differences between the gate electrodes by properly arranging the dummy electrode; and thus, it is possible to obtain desired transistor characteristics.
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