| 摘要 |
A processor architecture for providing many-to-one mappings between logical registers and physical registers, so that more than one logical register may map to the same physical register. Each physical register has an associated counter to indicate whether the physical register is free. A counter is incremented each time a mapping is made to its associated physical register, and is decremented when that mapping is no longer needed. If a logical register named in a decoded instruction is predicted to have the same value as a value stored in a physical register, then the logical register is mapped to the physical register. |
