| 摘要 |
PURPOSE: A method for fabricating a cell transistor of a dynamic random access memory(DRAM) is provided to reduce a trap-assisted tunneling leakage current by increasing a channel length and by decreasing an electric field on the edge of a gate. CONSTITUTION: After an insulation part and a cell well(11) are formed on a substrate, a gate oxide layer(12) is grown on the cell well. A gate electrode(13) and a nitride layer(14) are deposited and the gate is patterned by using a mask. Ions are implanted into the cell well to form a source/drain(15). A gate sidewall(17) is formed on the resultant structure having the source/drain by using a nitride layer and the surface of the source/drain is over-etched. A nitride layer is deposited on the resultant structure and is etched to form the first barrier sidewall(18). An interlayer dielectric oxide layer(19) is deposited on the resultant structure. The interlayer dielectric oxide layer in a contact hole is removed by using a mask. High doped n-polysilicon is filled in the contact hole from which the interlayer dielectric oxide layer is removed, so that a contact part is formed. N-polysilicon in the contact part is removed and the source/drain is over-etched. The second sidewall of a cylindrical type is formed only in the contact part by using an insulation layer. High doped polysilicon is filled to form a contact.
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