SEMICONDUCTOR MEMORY DEVICE HAVING DECOUPLING CAPACITOR

摘要

PURPOSE: A semiconductor memory device having a decoupling capacitor is provided to stabilize power of the semiconductor memory device by using a capacitor for stabilizing a low level of a word line. CONSTITUTION: A power decoupling capacitor is located between a node as a low level of a word line and a ground voltage(VSS) as a stabilized node. The power decoupling capacitor is formed by performing a fabrication process of a cell capacitor of a DRAM memory cell instead of the fabrication process of a gate capacitor using an existing MOS transistor. The cell capacitor of the memory cell as a data storage unit of the DRAM is formed by using a stacked poly capacitor or a trench capacitor in order to increase storage capacity. A thin insulating material is inserted between layers of the stacked poly capacitor or the trench capacitor. The electric field between two conductors forming the stacked poly capacitor or the trench capacitor is reduced and reliability of the decoupling capacitor is increased since a voltage difference between the node as the low level of the word line and the ground voltage(VSS) as the stabilized node is 0 or very small.