Delay locked loop for generating complementary clock signals

摘要

A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary delayed clock signals, provision is made of switching elements, which tap off the clock signal to be delayed along the series circuit of delay elements. Each of the delay elements has a series circuit of two inverters. One of the delayed clock signals is tapped off in each case at the output of the second of the inverters of the delay elements, and the complementary output signal from the delayed output signals is tapped off at the first of the inverters. What is thus made possible is that, disregarding the frequency of the clock signal to be delayed and the length of the delay time, the complementary delayed clock signals always have the same phase angle with respect to one another.