发明名称 Structure and methods for process integration in vertical DRAM cell fabrication
摘要 A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
申请公布号 US2003003653(A1) 申请公布日期 2003.01.02
申请号 US20010895672 申请日期 2001.06.29
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 MALIK RAJEEV;NESBIT LARRY;BEINTNER JOCHEN;DIVAKARUNI RAMA
分类号 H01L21/762;H01L21/8242;(IPC1-7):H01L21/823;H01L21/824;H01L21/20 主分类号 H01L21/762
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