发明名称 Substrate with top-flattened solder bumps and method for manufacturing the same
摘要 A method for manufacturing a wiring substrate includes the steps of applying, through printing, solder paste onto a plurality of pads exposed from the main surface of the substrate; melting the applied solder paste through reflowing, so as to form substantially hemispherical solder bumps; and flattening top portions of the substantially hemispherical solder bumps through the pressing of a flat pressing surface against the top portions, thereby forming top-flattened solder bumps. A pad is classified as a first pad when the pad is located within a region above a solid layer, and as a second pad when the pad is located outside of this region. In the solder paste application step, the amount of solder paste applied onto each first pad is smaller than that of solder paste applied onto each second pad.
申请公布号 US2003003706(A1) 申请公布日期 2003.01.02
申请号 US20020180965 申请日期 2002.06.27
申请人 SUZUKI TOMOE 发明人 SUZUKI TOMOE
分类号 H01L21/48;H05K1/11;H05K3/34;H05K3/46;(IPC1-7):H01L21/44;H01L21/50 主分类号 H01L21/48
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