| 发明名称 |
CURRENT LEAKAGE REDUCTION FOR LOADED BIT-LINES IN ON-CHIP MEMORY STRUCTURES |
| 摘要 |
Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
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| 申请公布号 |
US2003002322(A1) |
申请公布日期 |
2003.01.02 |
| 申请号 |
US20010896348 |
申请日期 |
2001.06.28 |
| 申请人 |
ALVANDPOUR ATILA;KRISHNAMURTHY RAM K.;NARENDRA SIVA G. |
发明人 |
ALVANDPOUR ATILA;KRISHNAMURTHY RAM K.;NARENDRA SIVA G. |
| 分类号 |
G11C11/412;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/412 |
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