| 发明名称 |
Reduced terminal testing system |
| 摘要 |
A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. |
| 申请公布号 |
US2003003606(A1) |
申请公布日期 |
2003.01.02 |
| 申请号 |
US20020212899 |
申请日期 |
2002.08.05 |
| 申请人 |
FARNWORTH WARREN M.;NEVILL LELAND R.;BEFFA RAYMOND J.;CLOUD EUGENE H. |
发明人 |
FARNWORTH WARREN M.;NEVILL LELAND R.;BEFFA RAYMOND J.;CLOUD EUGENE H. |
| 分类号 |
G01R31/02;G01R31/26;G01R31/28;G01R31/317;G01R31/3185;H01L21/00;H01L21/8238;H01L23/58;H01L27/10;H01L29/00;(IPC1-7):H01L21/00 |
主分类号 |
G01R31/02 |
| 代理机构 |
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