| 摘要 |
<p>A data processing apparatus (100) varying width data sizes for a data storing device is disclosed and may include a data storage circuit (201), a read/write switch circuit (103), an address generating circuit (104), and a selection signal generating circuit (202). Data storage circuit (201) may include at least one memory array (112), a selecting circuit (211 and 212), a read circuit (214) and a write circuit (213). Selecting circuit (211 and 212) may select a plurality of data bits from the memory array (112) in a first mode and may select N times the plurality of data bits from the memory array (112) in a second mode. Thus, the data storage circuit (201) may be shared by, for example, processors having different data widths. <IMAGE></p> |
