发明名称 Associative memory with AND gate match signal combining circuitry
摘要 An associative memory comprises an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.
申请公布号 EP1271548(A1) 申请公布日期 2003.01.02
申请号 EP20010305439 申请日期 2001.06.22
申请人 STMICROELECTRONICS, LTD. 发明人 BARNES, WILLIAM
分类号 G11C15/00;G11C15/04;(IPC1-7):G11C15/00 主分类号 G11C15/00
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